\entry{mach{\_}msg}{14}{\code {mach_msg}}
\entry{natural{\_}t}{15}{\code {natural_t}}
\entry{mach{\_}port{\_}t}{15}{\code {mach_port_t}}
\entry{mach{\_}msg{\_}bits{\_}t}{15}{\code {mach_msg_bits_t}}
\entry{mach{\_}msg{\_}size{\_}t}{15}{\code {mach_msg_size_t}}
\entry{mach{\_}msg{\_}id{\_}t}{15}{\code {mach_msg_id_t}}
\entry{mach{\_}msg{\_}header{\_}t}{15}{\code {mach_msg_header_t}}
\entry{MACH{\_}MSGH{\_}BITS}{16}{\code {MACH_MSGH_BITS}}
\entry{MACH{\_}MSGH{\_}BITS{\_}REMOTE}{17}{\code {MACH_MSGH_BITS_REMOTE}}
\entry{MACH{\_}MSGH{\_}BITS{\_}LOCAL}{17}{\code {MACH_MSGH_BITS_LOCAL}}
\entry{MACH{\_}MSGH{\_}BITS{\_}PORTS}{17}{\code {MACH_MSGH_BITS_PORTS}}
\entry{MACH{\_}MSGH{\_}BITS{\_}OTHER}{17}{\code {MACH_MSGH_BITS_OTHER}}
\entry{mach{\_}msg{\_}type{\_}name{\_}t}{17}{\code {mach_msg_type_name_t}}
\entry{mach{\_}msg{\_}type{\_}size{\_}t}{17}{\code {mach_msg_type_size_t}}
\entry{mach{\_}msg{\_}type{\_}number{\_}t}{17}{\code {mach_msg_type_number_t}}
\entry{mach{\_}msg{\_}type{\_}t}{17}{\code {mach_msg_type_t}}
\entry{MACH{\_}MSG{\_}TYPE{\_}PORT{\_}ANY}{19}{\code {MACH_MSG_TYPE_PORT_ANY}}
\entry{MACH{\_}MSG{\_}TYPE{\_}PORT{\_}ANY{\_}SEND}{19}{\code {MACH_MSG_TYPE_PORT_ANY_SEND}}
\entry{MACH{\_}MSG{\_}TYPE{\_}PORT{\_}ANY{\_}RIGHT}{19}{\code {MACH_MSG_TYPE_PORT_ANY_RIGHT}}
\entry{mach{\_}msg{\_}type{\_}long{\_}t}{19}{\code {mach_msg_type_long_t}}
\entry{mach{\_}port{\_}allocate}{29}{\code {mach_port_allocate}}
\entry{mach{\_}reply{\_}port}{30}{\code {mach_reply_port}}
\entry{mach{\_}port{\_}allocate{\_}name}{30}{\code {mach_port_allocate_name}}
\entry{mach{\_}port{\_}deallocate}{31}{\code {mach_port_deallocate}}
\entry{mach{\_}port{\_}destroy}{31}{\code {mach_port_destroy}}
\entry{mach{\_}port{\_}names}{32}{\code {mach_port_names}}
\entry{mach{\_}port{\_}type}{32}{\code {mach_port_type}}
\entry{mach{\_}port{\_}rename}{33}{\code {mach_port_rename}}
\entry{mach{\_}port{\_}get{\_}refs}{33}{\code {mach_port_get_refs}}
\entry{mach{\_}port{\_}mod{\_}refs}{34}{\code {mach_port_mod_refs}}
\entry{mach{\_}port{\_}insert{\_}right}{35}{\code {mach_port_insert_right}}
\entry{mach{\_}port{\_}extract{\_}right}{35}{\code {mach_port_extract_right}}
\entry{mach{\_}port{\_}seqno{\_}t}{36}{\code {mach_port_seqno_t}}
\entry{mach{\_}port{\_}mscount{\_}t}{36}{\code {mach_port_mscount_t}}
\entry{mach{\_}port{\_}msgcount{\_}t}{36}{\code {mach_port_msgcount_t}}
\entry{mach{\_}port{\_}rights{\_}t}{36}{\code {mach_port_rights_t}}
\entry{mach{\_}port{\_}status{\_}t}{36}{\code {mach_port_status_t}}
\entry{mach{\_}port{\_}get{\_}receive{\_}status}{37}{\code {mach_port_get_receive_status}}
\entry{mach{\_}port{\_}set{\_}mscount}{37}{\code {mach_port_set_mscount}}
\entry{mach{\_}port{\_}set{\_}qlimit}{37}{\code {mach_port_set_qlimit}}
\entry{mach{\_}port{\_}set{\_}seqno}{38}{\code {mach_port_set_seqno}}
\entry{mach{\_}port{\_}get{\_}set{\_}status}{38}{\code {mach_port_get_set_status}}
\entry{mach{\_}port{\_}move{\_}member}{38}{\code {mach_port_move_member}}
\entry{mach{\_}port{\_}request{\_}notification}{39}{\code {mach_port_request_notification}}
\entry{vm{\_}allocate}{41}{\code {vm_allocate}}
\entry{vm{\_}deallocate}{41}{\code {vm_deallocate}}
\entry{vm{\_}read}{42}{\code {vm_read}}
\entry{vm{\_}write}{42}{\code {vm_write}}
\entry{vm{\_}copy}{43}{\code {vm_copy}}
\entry{vm{\_}region}{43}{\code {vm_region}}
\entry{vm{\_}protect}{43}{\code {vm_protect}}
\entry{vm{\_}inherit}{44}{\code {vm_inherit}}
\entry{vm{\_}wire}{44}{\code {vm_wire}}
\entry{vm{\_}machine{\_}attribute}{45}{\code {vm_machine_attribute}}
\entry{vm{\_}map}{46}{\code {vm_map}}
\entry{vm{\_}statistics{\_}data{\_}t}{47}{\code {vm_statistics_data_t}}
\entry{vm{\_}statistics}{48}{\code {vm_statistics}}
\entry{memory{\_}object{\_}server}{49}{\code {memory_object_server}}
\entry{memory{\_}object{\_}default{\_}server}{49}{\code {memory_object_default_server}}
\entry{seqnos{\_}memory{\_}object{\_}server}{49}{\code {seqnos_memory_object_server}}
\entry{seqnos{\_}memory{\_}object{\_}default{\_}server}{49}{\code {seqnos_memory_object_default_server}}
\entry{memory{\_}object{\_}init}{49}{\code {memory_object_init}}
\entry{seqnos{\_}memory{\_}object{\_}init}{50}{\code {seqnos_memory_object_init}}
\entry{memory{\_}object{\_}ready}{50}{\code {memory_object_ready}}
\entry{memory{\_}object{\_}terminate}{51}{\code {memory_object_terminate}}
\entry{seqnos{\_}memory{\_}object{\_}terminate}{51}{\code {seqnos_memory_object_terminate}}
\entry{memory{\_}object{\_}destroy}{51}{\code {memory_object_destroy}}
\entry{memory{\_}object{\_}data{\_}return}{52}{\code {memory_object_data_return}}
\entry{seqnos{\_}memory{\_}object{\_}data{\_}return}{52}{\code {seqnos_memory_object_data_return}}
\entry{memory{\_}object{\_}data{\_}request}{52}{\code {memory_object_data_request}}
\entry{seqnos{\_}memory{\_}object{\_}data{\_}request}{52}{\code {seqnos_memory_object_data_request}}
\entry{memory{\_}object{\_}data{\_}supply}{53}{\code {memory_object_data_supply}}
\entry{memory{\_}object{\_}supply{\_}completed}{53}{\code {memory_object_supply_completed}}
\entry{seqnos{\_}memory{\_}object{\_}supply{\_}completed}{54}{\code {seqnos_memory_object_supply_completed}}
\entry{memory{\_}object{\_}data{\_}error}{54}{\code {memory_object_data_error}}
\entry{memory{\_}object{\_}data{\_}unavailable}{54}{\code {memory_object_data_unavailable}}
\entry{memory{\_}object{\_}copy}{55}{\code {memory_object_copy}}
\entry{seqnos{\_}memory{\_}object{\_}copy}{55}{\code {seqnos_memory_object_copy}}
\entry{memory{\_}object{\_}data{\_}provided}{56}{\code {memory_object_data_provided}}
\entry{memory{\_}object{\_}lock{\_}request}{56}{\code {memory_object_lock_request}}
\entry{memory{\_}object{\_}lock{\_}completed}{57}{\code {memory_object_lock_completed}}
\entry{seqnos{\_}memory{\_}object{\_}lock{\_}completed}{57}{\code {seqnos_memory_object_lock_completed}}
\entry{memory{\_}object{\_}data{\_}unlock}{57}{\code {memory_object_data_unlock}}
\entry{seqnos{\_}memory{\_}object{\_}data{\_}unlock}{57}{\code {seqnos_memory_object_data_unlock}}
\entry{memory{\_}object{\_}get{\_}attributes}{58}{\code {memory_object_get_attributes}}
\entry{memory{\_}object{\_}change{\_}attributes}{58}{\code {memory_object_change_attributes}}
\entry{memory{\_}object{\_}change{\_}completed}{59}{\code {memory_object_change_completed}}
\entry{seqnos{\_}memory{\_}object{\_}change{\_}completed}{59}{\code {seqnos_memory_object_change_completed}}
\entry{vm{\_}set{\_}default{\_}memory{\_}manager}{59}{\code {vm_set_default_memory_manager}}
\entry{memory{\_}object{\_}create}{59}{\code {memory_object_create}}
\entry{seqnos{\_}memory{\_}object{\_}create}{59}{\code {seqnos_memory_object_create}}
\entry{memory{\_}object{\_}data{\_}initialize}{60}{\code {memory_object_data_initialize}}
\entry{seqnos{\_}memory{\_}object{\_}data{\_}initialize}{60}{\code {seqnos_memory_object_data_initialize}}
\entry{thread{\_}create}{61}{\code {thread_create}}
\entry{thread{\_}terminate}{61}{\code {thread_terminate}}
\entry{mach{\_}thread{\_}self}{61}{\code {mach_thread_self}}
\entry{thread{\_}info}{62}{\code {thread_info}}
\entry{struct thread{\_}basic{\_}info}{62}{\code {struct thread_basic_info}}
\entry{thread{\_}basic{\_}info{\_}t}{63}{\code {thread_basic_info_t}}
\entry{struct thread{\_}sched{\_}info}{63}{\code {struct thread_sched_info}}
\entry{thread{\_}sched{\_}info{\_}t}{64}{\code {thread_sched_info_t}}
\entry{thread{\_}wire}{64}{\code {thread_wire}}
\entry{thread{\_}suspend}{64}{\code {thread_suspend}}
\entry{thread{\_}resume}{65}{\code {thread_resume}}
\entry{thread{\_}abort}{65}{\code {thread_abort}}
\entry{thread{\_}get{\_}state}{66}{\code {thread_get_state}}
\entry{thread{\_}set{\_}state}{66}{\code {thread_set_state}}
\entry{thread{\_}priority}{67}{\code {thread_priority}}
\entry{thread{\_}max{\_}priority}{67}{\code {thread_max_priority}}
\entry{thread{\_}switch}{67}{\code {thread_switch}}
\entry{thread{\_}depress{\_}abort}{68}{\code {thread_depress_abort}}
\entry{swtch}{68}{\code {swtch}}
\entry{swtch{\_}pri}{69}{\code {swtch_pri}}
\entry{thread{\_}policy}{69}{\code {thread_policy}}
\entry{thread{\_}get{\_}special{\_}port}{69}{\code {thread_get_special_port}}
\entry{thread{\_}get{\_}kernel{\_}port}{69}{\code {thread_get_kernel_port}}
\entry{thread{\_}get{\_}exception{\_}port}{69}{\code {thread_get_exception_port}}
\entry{thread{\_}set{\_}special{\_}port}{70}{\code {thread_set_special_port}}
\entry{thread{\_}set{\_}kernel{\_}port}{70}{\code {thread_set_kernel_port}}
\entry{thread{\_}set{\_}exception{\_}port}{70}{\code {thread_set_exception_port}}
\entry{catch{\_}exception{\_}raise}{70}{\code {catch_exception_raise}}
\entry{exception{\_}raise}{70}{\code {exception_raise}}
\entry{evc{\_}wait}{70}{\code {evc_wait}}
\entry{task{\_}create}{70}{\code {task_create}}
\entry{task{\_}terminate}{71}{\code {task_terminate}}
\entry{mach{\_}task{\_}self}{71}{\code {mach_task_self}}
\entry{task{\_}threads}{71}{\code {task_threads}}
\entry{task{\_}info}{72}{\code {task_info}}
\entry{struct task{\_}basic{\_}info}{72}{\code {struct task_basic_info}}
\entry{task{\_}basic{\_}info{\_}t}{73}{\code {task_basic_info_t}}
\entry{struct task{\_}events{\_}info}{73}{\code {struct task_events_info}}
\entry{task{\_}events{\_}info{\_}t}{73}{\code {task_events_info_t}}
\entry{struct task{\_}thread{\_}times{\_}info}{73}{\code {struct task_thread_times_info}}
\entry{task{\_}thread{\_}times{\_}info{\_}t}{74}{\code {task_thread_times_info_t}}
\entry{task{\_}suspend}{74}{\code {task_suspend}}
\entry{task{\_}resume}{74}{\code {task_resume}}
\entry{task{\_}priority}{74}{\code {task_priority}}
\entry{task{\_}ras{\_}control}{74}{\code {task_ras_control}}
\entry{task{\_}get{\_}special{\_}port}{75}{\code {task_get_special_port}}
\entry{task{\_}get{\_}kernel{\_}port}{76}{\code {task_get_kernel_port}}
\entry{task{\_}get{\_}exception{\_}port}{76}{\code {task_get_exception_port}}
\entry{task{\_}get{\_}bootstrap{\_}port}{76}{\code {task_get_bootstrap_port}}
\entry{task{\_}set{\_}special{\_}port}{76}{\code {task_set_special_port}}
\entry{task{\_}set{\_}kernel{\_}port}{76}{\code {task_set_kernel_port}}
\entry{task{\_}set{\_}exception{\_}port}{76}{\code {task_set_exception_port}}
\entry{task{\_}set{\_}bootstrap{\_}port}{76}{\code {task_set_bootstrap_port}}
\entry{task{\_}get{\_}emulation{\_}vector}{77}{\code {task_get_emulation_vector}}
\entry{task{\_}set{\_}emulation{\_}vector}{77}{\code {task_set_emulation_vector}}
\entry{task{\_}set{\_}emulation}{77}{\code {task_set_emulation}}
\entry{task{\_}enable{\_}pc{\_}sampling}{77}{\code {task_enable_pc_sampling}}
\entry{thread{\_}enable{\_}pc{\_}sampling}{77}{\code {thread_enable_pc_sampling}}
\entry{task{\_}disable{\_}pc{\_}sampling}{77}{\code {task_disable_pc_sampling}}
\entry{thread{\_}disable{\_}pc{\_}sampling}{77}{\code {thread_disable_pc_sampling}}
\entry{task{\_}get{\_}sampled{\_}pcs}{78}{\code {task_get_sampled_pcs}}
\entry{thread{\_}get{\_}sampled{\_}pcs}{78}{\code {thread_get_sampled_pcs}}
\entry{sample{\_}pc{\_}t}{78}{\code {sample_pc_t}}
\entry{sample{\_}pc{\_}flavor{\_}t}{78}{\code {sample_pc_flavor_t}}
\entry{mach{\_}host{\_}self}{81}{\code {mach_host_self}}
\entry{host{\_}info}{81}{\code {host_info}}
\entry{struct host{\_}basic{\_}info}{82}{\code {struct host_basic_info}}
\entry{host{\_}basic{\_}info{\_}t}{82}{\code {host_basic_info_t}}
\entry{struct host{\_}sched{\_}info}{82}{\code {struct host_sched_info}}
\entry{host{\_}sched{\_}info{\_}t}{83}{\code {host_sched_info_t}}
\entry{host{\_}kernel{\_}version}{83}{\code {host_kernel_version}}
\entry{host{\_}get{\_}boot{\_}info}{83}{\code {host_get_boot_info}}
\entry{time{\_}value{\_}t}{83}{\code {time_value_t}}
\entry{time{\_}value{\_}add{\_}usec}{83}{\code {time_value_add_usec}}
\entry{time{\_}value{\_}add}{83}{\code {time_value_add}}
\entry{host{\_}get{\_}time}{84}{\code {host_get_time}}
\entry{host{\_}set{\_}time}{84}{\code {host_set_time}}
\entry{host{\_}adjust{\_}time}{84}{\code {host_adjust_time}}
\entry{mapped{\_}time{\_}value{\_}t}{84}{\code {mapped_time_value_t}}
\entry{host{\_}reboot}{84}{\code {host_reboot}}
\entry{host{\_}processor{\_}sets}{87}{\code {host_processor_sets}}
\entry{host{\_}processor{\_}set{\_}priv}{87}{\code {host_processor_set_priv}}
\entry{processor{\_}set{\_}default}{87}{\code {processor_set_default}}
\entry{processor{\_}set{\_}create}{87}{\code {processor_set_create}}
\entry{processor{\_}set{\_}destroy}{88}{\code {processor_set_destroy}}
\entry{processor{\_}set{\_}tasks}{88}{\code {processor_set_tasks}}
\entry{processor{\_}set{\_}threads}{88}{\code {processor_set_threads}}
\entry{task{\_}assign}{88}{\code {task_assign}}
\entry{task{\_}assign{\_}default}{89}{\code {task_assign_default}}
\entry{task{\_}get{\_}assignment}{89}{\code {task_get_assignment}}
\entry{thread{\_}assign}{89}{\code {thread_assign}}
\entry{thread{\_}assign{\_}default}{89}{\code {thread_assign_default}}
\entry{thread{\_}get{\_}assignment}{89}{\code {thread_get_assignment}}
\entry{processor{\_}set{\_}max{\_}priority}{90}{\code {processor_set_max_priority}}
\entry{processor{\_}set{\_}policy{\_}enable}{90}{\code {processor_set_policy_enable}}
\entry{processor{\_}set{\_}policy{\_}disable}{90}{\code {processor_set_policy_disable}}
\entry{processor{\_}set{\_}info}{91}{\code {processor_set_info}}
\entry{struct processor{\_}set{\_}basic{\_}info}{91}{\code {struct processor_set_basic_info}}
\entry{processor{\_}set{\_}basic{\_}info{\_}t}{92}{\code {processor_set_basic_info_t}}
\entry{struct processor{\_}set{\_}sched{\_}info}{92}{\code {struct processor_set_sched_info}}
\entry{processor{\_}set{\_}sched{\_}info{\_}t}{92}{\code {processor_set_sched_info_t}}
\entry{host{\_}processors}{92}{\code {host_processors}}
\entry{processor{\_}start}{92}{\code {processor_start}}
\entry{processor{\_}exit}{92}{\code {processor_exit}}
\entry{processor{\_}control}{92}{\code {processor_control}}
\entry{processor{\_}assign}{93}{\code {processor_assign}}
\entry{processor{\_}get{\_}assignment}{93}{\code {processor_get_assignment}}
\entry{processor{\_}info}{93}{\code {processor_info}}
\entry{struct processor{\_}basic{\_}info}{94}{\code {struct processor_basic_info}}
\entry{processor{\_}basic{\_}info{\_}t}{94}{\code {processor_basic_info_t}}
\entry{device{\_}reply{\_}server}{95}{\code {device_reply_server}}
\entry{device{\_}open}{95}{\code {device_open}}
\entry{device{\_}open{\_}request}{96}{\code {device_open_request}}
\entry{ds{\_}device{\_}open{\_}reply}{96}{\code {ds_device_open_reply}}
\entry{device{\_}close}{96}{\code {device_close}}
\entry{device{\_}read}{96}{\code {device_read}}
\entry{device{\_}read{\_}inband}{97}{\code {device_read_inband}}
\entry{device{\_}read{\_}request}{97}{\code {device_read_request}}
\entry{ds{\_}device{\_}read{\_}reply}{97}{\code {ds_device_read_reply}}
\entry{device{\_}read{\_}request{\_}inband}{97}{\code {device_read_request_inband}}
\entry{ds{\_}device{\_}read{\_}reply{\_}inband}{97}{\code {ds_device_read_reply_inband}}
\entry{device{\_}write}{97}{\code {device_write}}
\entry{device{\_}write{\_}inband}{98}{\code {device_write_inband}}
\entry{device{\_}write{\_}request}{98}{\code {device_write_request}}
\entry{ds{\_}device{\_}write{\_}reply}{98}{\code {ds_device_write_reply}}
\entry{device{\_}write{\_}request{\_}inband}{98}{\code {device_write_request_inband}}
\entry{ds{\_}device{\_}write{\_}reply{\_}inband}{98}{\code {ds_device_write_reply_inband}}
\entry{device{\_}map}{98}{\code {device_map}}
\entry{device{\_}set{\_}status}{99}{\code {device_set_status}}
\entry{device{\_}get{\_}status}{99}{\code {device_get_status}}
\entry{device{\_}set{\_}filter}{99}{\code {device_set_filter}}