@Bibtex-file{SE/formal.hardware.verification.bib,
  title =        "Bibliography on Hardware Verification and Formal
                 Methods",
  author =       "Hardware Verification Group",
  address =      "Hardware Verification Group at the Institute of
                 Computer Design and Fault Tolerance\\ Department of
                 Computer Science\\ University of Karlsruhe\\ Germany",
  supported =    "yes",
  abstract =     "This is a reference list on hardware verification and
                 formal methods in general.",
  readme =       "Feel free to use, copy, alter or redistribute this
                 file, but please include proper acknowledgement.\\
                 Realize that it is by no means a complete or exhaustive
                 list. Comments, corrections and additions can be sent
                 to kropf@informatik.uni-karlsruhe.de.",
  keywords =     "ADL, abstraction, algorithmiclevel, asynchronous,
                 automation, BDD, Benchmarks, CAPRA, circuits,
                 classification of properties, compiler, complexity,
                 concurrent programs, CONLAN, ctl, cve, DDL, Design,
                 ELLA, eventstructure, fair transition system, fairness,
                 finite-state system, firstorderlogic, flowgraph, formal
                 methods, formalism, formalsynthesis, fsm, gatelevel,
                 general, graph, hardware, HDL, higherorderlogic, HOL,
                 HOL-System, itl, KARL, layout, layoutlevel, liveness,
                 Logic, ltl, Methods, microprocessor, ML, modelchecking,
                 modelling, omega, omegafsm, optimization, other,
                 petrinet, processalgebra, program verification,
                 progress, PROLOG, proof systems, propositionallogic,
                 reachability analysis, reactive systems, realtime,
                 recurrence, refinement, registertransferlevel,
                 responsiveness, Rewrite, rewriting, RISC, safety,
                 SFB358, shortest path, SILAGE, simulation, SMAX, SML,
                 software, softwareverification, specification, survey,
                 switchlevel, symbolic state traversal,
                 symbolicsimulation, synthesis, system, systemlevel,
                 techreport, temporallogic, test, textbook, theorem
                 proving, timers, timing, tpcd94, trace,
                 trajectoryevaluation, transistorlevel, transition,
                 transitionsystem, transitionsystemfair,
                 transitionsystemlabelled, transpositionsystem,
                 tutorial, UNITY, verification, verificationformalism,
                 VHDL, VIOLA, voss",
}